Altera Complete Design Suite v11.0 SP1 LINUX-SPYRAL(2011) | 7.73 GB
PROUDLY PRESENTS
Altera Complete Design Suite v11.0 SP1
(c) Altera
Type ..... : FPGA
Date ..... : 08/2011
Size ..... : 84x100MB
OS ....... : Linux 32/64bit
RELEASE NOTES
ModelSim-Altera Edition is recommended for simulating all FPGA designs
(Cyclone, Arria, and Stratix series FPGA designs)
DSP Builder technology allows you to go from system definition and simulation using the industry-standard MathWorks Simulink tools to system implementation in a matter of minutes. The DSP Builder Signal Compiler block reads Simulink Model Files (.mdl) that are built using DSP Builder and MegaCore blocks and generates VHDL files and Tcl scripts for synthesis, hardware implementation, and simulation.
The Nios II Embedded Design Suite (EDS) is a collection of cutting-edge software tools, utilities, libraries, and drivers to help you bring your design to market in record time.
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